Fuse structure and manufacturing method thereof

ABSTRACT

A fuse structure and a manufacturing method thereof are provided. The fuse structure includes: a substrate; an active region positioned above the substrate; a fuse gate structure surrounding a circumferential outer surface of the active region and electrically connected to a first power source; and a control gate structure surrounding a circumferential outer surface of the fuse gate structure and electrically connected to a second power source. A voltage of the first power source is greater than that of the second power source.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of PCT/CN2021/120280, filed on Sep.24, 2021, which claims priority to Chinese Patent Application No.2021105532758 titled “FUSE STRUCTURE AND MANUFACTURING METHOD THEREOF”and filed on May 20, 2021, the entire contents of which are incorporatedherein by reference.

TECHNICAL FIELD

The present disclosure relates to a fuse structure and a manufacturingmethod thereof.

BACKGROUND

A fuse memory cell is widely used for repair work in integratedcircuits, and its classic structures include control gate structures anddiscrete fuse gate structures.

SUMMARY

According to a plurality of embodiments, a first aspect of the presentdisclosure provides a fuse structure, which includes:

a substrate;

an active region positioned above the substrate;

a fuse gate structure surrounding a circumferential outer surface of theactive region and electrically connected to a first power source; and

a control gate structure surrounding a circumferential outer surface ofthe fuse gate structure and electrically connected to a second powersource.

A voltage of the first power source is greater than that of the secondpower source.

A method for manufacturing a fuse structure includes:

providing a substrate;

forming an active region above the substrate;

forming a fuse gate structure on a circumferential outer surface of theactive region, the fuse gate structure being electrically connected to afirst power source; and

forming a control gate structure on a circumferential outer surface ofthe fuse gate structure, the control gate structure being electricallyconnected to a second power source.

A voltage of the first power source is greater than that of the secondpower source.

Details of one or more embodiments of the present disclosure are setforth in the following drawings and descriptions. Other features andadvantages of the present disclosure will become apparent fromspecification, drawings and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

To describe the technical solutions in the embodiments of the presentdisclosure or the existing technologies more clearly, the accompanyingdrawings required for describing the embodiments or the existingtechnologies will be briefly introduced below. Apparently, theaccompanying drawings in the following description are merely someembodiments of the present disclosure. To those of ordinary skills inthe art, other accompanying drawings may also be derived from theseaccompanying drawings without creative efforts.

FIG. 1 is a three-dimensional schematic diagram of a fuse structureaccording to an embodiment.

FIG. 2 is a schematic cross-sectional view of the fuse structureprovided in FIG. 1 along an AA′ direction;

FIG. 3 is a three-dimensional schematic diagram of a fuse structureaccording to another embodiment;

FIG. 4 is a schematic cross-sectional view of the fuse structureprovided in FIG. 1 along a BB′ direction; and

FIG. 5 is a flowchart of a method for manufacturing a fuse structureaccording to an embodiment.

REFERENCE NUMBERS IN THE ACCOMPANYING DRAWINGS

100—substrate; 200—active region; 300—fuse gate structure; 310—firstgate dielectric layer; 320—fuse gate layer; 400—control gate structure;410—second gate dielectric layer; 420—control gate layer; 500—sourceregion; 600—drain region; 700—fuse connection end; 800—controlconnection end, 910—source connection end; and 920—drain connection end.

DETAILED DESCRIPTION

Limited by design rules between two gate structures, the fuse structuredescribed in the background art has a problem of overlarge area. Asintegration of integrated circuits continues to increase, disadvantagesof the overlarge area will gradually appear.

For ease of understanding the present disclosure, the present disclosurewill be described more fully hereinafter with reference to theaccompanying drawings. Some embodiments of the present disclosure areprovided in the accompanying drawings. The present disclosure may,however, be embodied in many different forms and should not be limitedto the embodiments set forth herein. Rather, these embodiments areprovided so that the present disclosure will be more thorough andcomplete.

Unless otherwise defined, all technical and scientific terms employedherein have the same meaning as commonly understood by one of ordinaryskill in the art to which the present disclosure belongs. The termsemployed in the specification of the present disclosure are merely forthe purpose of describing some embodiments and are not intended forlimiting the present disclosure.

It should be understood that when an element or layer is referred to asbeing “on”, “adjacent to”, “connected to” or “coupled to” other elementsor layers, it may be directly on, adjacent to, connected or coupled tothe other elements or layers, or intervening elements or layers may bepresent. In contrast, when an element is referred to as being “directlyon”, “directly adjacent to”, “directly connected to” or “directlycoupled to” other elements or layers, there are no intervening elementsor layers present. It should be understood that although the termsfirst, second, third, etc. may be employed to describe various elements,components, regions, layers, doping types and/or sections, theseelements, components, regions, layers, doping types and/or sectionsshould not be limited by these terms. These terms are only employed todistinguish one element, component, region, layer, doping type, orsection from another element, component, region, layer, doping type, orsection. Therefore, without departing from the teachings of the presentdisclosure, a first element, component, region, layer, doping type, orsection discussed below may be represented as a second element,component, region, layer, doping type, or section.

Spatially relative terms such as “below”, “under”, “lower”, “beneath”,“above”, “upper” and the like may be used herein to describerelationships between one element or feature as shown in the figures andanother element(s) or feature(s). It should be understood that thespatially relative terms may be intended to encompass differentorientations of a device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements or features described as “under”,“beneath” or “below” other elements would then be oriented “above” theother elements or features. Thus, the example term “under”, “below” or“beneath” may encompass both an orientation of above and below. Inaddition, the device may also be otherwise oriented (for example,rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein should be interpreted accordingly.

As used herein, the singular forms of “a”, “one” and “said/the” are alsointended to include plural forms, unless the context clearly indicatesotherwise. It should also be understood that the terms “comprising”and/or “including”, when used in this specification, may determine thepresence of the described features, integers, steps, operations,elements and/or components, but do not preclude the presence or additionof one or more other features, integers, steps, operations, elements,components, and/or groups thereof. Meanwhile, as used herein, the term“and/or” includes any and all combinations of related listed items.

Embodiments of the present disclosure are described herein withreference to cross-sectional illustrations serving as schematicillustrations of idealized embodiments (and intermediate structures) ofthe present disclosure. As such, variations from the shapes of theillustrations as a result, for example, of manufacturing techniquesand/or tolerances, may be expected. Thus, the embodiments of the presentdisclosure should not be construed as being limited to particular shapesof regions illustrated herein but may include deviations in shapes thatresult, for example, from the manufacturing techniques. Thus, regionsillustrated in the figures are schematic in nature and their shapes donot necessarily illustrate the actual shape of a region of the deviceand do not limit the scope of the present disclosure.

Referring to FIG. 1 and FIG. 2 (or referring to FIG. 3 and FIG. 4), thepresent disclosure provides a fuse structure, which includes a substrate100, an active region 200, a fuse gate structure 300, and a control gatestructure 400.

The substrate 100 includes, but is not limited to, a silicon substrate.The active region 200 is positioned above the substrate 100, and amaterial of the active region 200 may be the same as a material of thesubstrate 100 or may be different from the material of the substrate100, which is not limited in the present disclosure. In someembodiments, the material of the active region 200 may be silicon,silicon germanium, silicon carbide, or the like.

As an example, referring to FIG. 1 and FIG. 2, an extension direction ofthe active region 200 may be perpendicular to a surface of the substrate100. Moreover, the active region 200 may be connected to the substrate100.

At this moment, a source region 500 (or a drain region 600) may be firstformed in the substrate 100, and then the active region 200 is formedupward from the source region 500 (or the drain region 600). Next, thedrain region 600 (or the source region 500) is formed on a top of theactive region 200.

As another example, referring to FIG. 3 and FIG. 4, the extensiondirection of the active region 200 may be parallel to the surface of thesubstrate 100. Moreover, the active region 200 may be spaced apart fromthe substrate 100.

At this moment, a fin-shaped region may be formed in the substrate 100.Two sides of the fin-shaped region may be respectively provided with ashallow trench isolation (STI) structure, wherein a material of the STIstructure may be silicon dioxide or the like. The active region 200 maybe positioned above the fin-shaped region.

In addition, at this moment, epitaxial growth may be performed on twosides of the active region 200 to form the source region 500 and thedrain region 600.

Of course, there may be more forms for arranging the active region 200above the substrate 100 (for example, the extension direction of theactive region 200 may also be at a certain oblique angle to the surfaceof the substrate 100), on which no excessive restrictions are imposed inthe present disclosure. In addition, there may be a variety of ways toform the source region 500 and the drain region 600. For example, thefuse gate structure 300 and the control gate structure 400 at leastcover a part of the active region 200, and two ends of the uncoveredactive region 200 may also be doped to form the source region 500 andthe drain region 600.

The fuse gate structure 300 surrounds a circumferential outer surface ofthe active region 200, and the control gate structure 400 surrounds acircumferential outer surface of the fuse gate structure 300. Here, itmay be understood that both the fuse gate structure 300 and the controlgate structure 400 are insulated from the source region 500 and thedrain region 600 on two sides. In some embodiments, an insulating layermay be respectively provided between the fuse gate structure 300 and thecontrol gate structure 400 and the source region 500 and the drainregion 600 on two sides.

In addition, the fuse gate structure 300 surrounds the circumferentialouter surface of the active region 200, and the control gate structure400 surrounds the circumferential outer surface of the fuse gatestructure 300. Therefore, the fuse gate structure 300 and the controlgate structure 400 jointly control formation of a conductive channel inthe active region 200. In some embodiments, the conductive channel maybe positioned near a circumferential outer surface of the active region200.

Furthermore, the fuse gate structure 300 is electrically connected to afirst power source, and the control gate structure 400 is electricallyconnected to a second power source, wherein a voltage of the first powersource is greater than that of the second power source.

When the fuse gate structure 300 receives the voltage of the first powersource, the fuse gate structure 300 may be broken down because thevoltage is relatively large. Electrical conductivity of the fuse gatestructure 300 broken down is changed, which in turn changes a size ofthe conductive channel formed in the active region 200, such that amagnitude of the source-drain current flowing through the conductivechannel may be changed.

In this way, discrimination between “0” and “1” may be realized bycontrolling ON and OFF of the first power source.

In some embodiments, in an application process of the fuse structure,reading different logic states “0” and “1” of the fuse structure may beimplemented by controlling ON and OFF of the first power source.

In addition, a reasonable second power source may be set, such that whenvarious logic states of the fuse structure are read to turn on thesecond power source, the conductive channel is formed in the activeregion 200, and then the logic states “0” and “1” are read based ondifferent source-drain currents.

It is worth noting that in the present disclosure, the fuse gatestructure 300 being electrically connected to the first power sourcemeans that the fuse gate structure 300 has the function of electricallyconnecting the first power source. However, in practical applications,it is needed to determine whether to obtain electrical signal connectionaccording to requirements. In some embodiments, a first switch may beprovided between the fuse gate structure 300 and the first power source.

Similarly, the control gate structure 400 being electrically connectedto the second power source means that the control gate structure 400 hasthe function of electrically connecting the second power source.However, in practical applications, it is needed to determine whether toobtain electrical signal connection according to requirements. In someembodiments, a second switch may be provided between the control gatestructure 400 and the second power source.

In this embodiment, the fuse gate structure 300 surrounds thecircumferential outer surface of the active region 200, and the controlgate structure 400 surrounds the circumferential outer surface of thefuse gate structure 300, such that the conductive channel may be formedin the circumferential outer surface of the active region 200, and thusarea can be effectively saved. Meanwhile, the control gate structure 400and the fuse gate structure 300 are stacked and arranged around, therebybeing combined into a single gate structure, so this embodiment cangreatly save area and greatly improve integration of a fuse circuit.

In one embodiment, referring to FIG. 2 or FIG. 4, the fuse gatestructure 300 includes a first gate dielectric layer 310 and a fuse gatelayer 320. The first gate dielectric layer 310 may be an insulatinglayer such as an oxide, and the first gate dielectric layer 310surrounds the circumferential outer surface of the active region 200.The fuse gate layer 320 may be a conductive layer such as polysilicon,and the fuse gate layer 320 surrounds a circumferential outer surface ofthe first gate dielectric layer 310 and is electrically connected to thefirst power source.

When the fuse gate layer 320 receives the voltage of the first powersource, the first gate dielectric layer 310 surrounded and covered bythe fuse gate layer 320 is broken down by a first gate voltage, suchthat resistance of the first gate dielectric layer 310 decreases, andthus a source-drain current increases.

The control gate structure 400 includes a second gate dielectric layer410 and a control gate layer 420. The second gate dielectric layer 410may be an insulating layer such as an oxide, and the second gatedielectric layer 410 surrounds a circumferential outer surface of thefuse gate layer 320. The control gate layer 420 may be a conductivelayer such as polysilicon, and the control gate layer 420 surrounds acircumferential outer surface of the second gate dielectric layer 410and is electrically connected to the second power source.

When the control gate layer 420 receives the voltage of the second powersource, a conductive channel in the active region 200 is formed.

It may be understood that a material of the first gate dielectric layer310 may be the same as or different from a material of the second gatedielectric layer 410, which is not limited in the present disclosure. Amaterial of the control gate layer 420 may be the same as or differentfrom a material of the fuse gate layer 320, which is also not limited inthe present disclosure.

In addition, the first gate dielectric layer 310, the second gatedielectric layer 410, the fuse gate layer 320 and the control gate layer420 may be a single-layer film layer structure or a multiple-layer filmlayer structure, which may be set according to actual needs. Forexample, the second gate dielectric layer 410 may include a high-Kdielectric layer such as hafnium oxide. In this case, the control gatelayer 420 may include a plurality of stacked metal layers.

Moreover, in addition to the second gate dielectric layer 410 and thecontrol gate layer 420, the control gate structure 400 may also includeother functional film layers. In addition to the first gate dielectriclayer 310 and the fuse gate layer 320, the fuse gate structure 300 mayalso include other functional film layers. However, the presentdisclosure is not limited thereto.

Further, in this embodiment, a thickness of the second gate dielectriclayer 410 may be greater than that of the first gate dielectric layer310.

Because the second gate dielectric layer 410 and the first gatedielectric layer 310 are respectively positioned on two sides of thefuse gate layer 320, when the first gate dielectric layer 310 is brokendown due to the fuse gate layer 320 receiving a voltage signal of thefirst power source, the second gate dielectric layer 410 may inevitablybe adversely impacted.

In this embodiment, by setting the thickness of the second gatedielectric layer 410 to be greater than that of the first gatedielectric layer 310, the adverse impact on the second gate dielectriclayer 410 when the first gate dielectric layer 310 is broken down can beeffectively reduced.

As an example, the thickness of the first gate dielectric layer 310 maybe set 1.5 nm to 2.5 nm, and the thickness of the second gate dielectriclayer 410 may be set 4.5 nm to 6 nm. In this way, it may be ensured thatthe second gate dielectric layer 410 is not to be damaged in the processof breaking down and fusing the first gate dielectric layer 310, therebyensuring reliability of products. At this moment, a voltage range of thefirst power source may be further set to 5V-6V, and a voltage range ofthe second power source may be set to 2V-3V.

Of course, in other embodiments, the second gate dielectric layer 410may also be protected in other ways. For example, a dielectric constantof the second gate dielectric layer 410 may be set to be greater thanthat of the first gate dielectric layer 310.

In one embodiment, referring to FIG. 1 and FIG. 2 (or referring to FIG.3 and FIG. 4), the fuse structure also includes a fuse connection end700 and a control connection end 800. The fuse connection end 700 isconnected to the fuse gate layer 320 to electrically connect the firstpower source. The control connection end 800 is connected to the controlgate layer 420 to electrically connect the second power source.

The fuse connection end 700 and the control connection end 800 arerespectively positioned on two opposite sides of the active region 200,which may effectively prevent signal coupling interference between thefuse connection end 700 and the control connection end 800.

Further, extension directions of the fuse connection end 700 and of thecontrol connection end 800 may be set to be perpendicular to theextension direction of the active region 200.

In this case, the fuse connection end 700 and the control connection end800 are far away from the source region 500 and the drain region 600 onthe two sides of the active region 200, such that signal interference tothe source region 500 and the drain region 600 may be reduced.

In some embodiments, referring to FIG. 1 and FIG. 2, when the extensiondirection of the active region 200 is perpendicular to the surface ofthe substrate 100, and the active region 200 is connected to thesubstrate 100, the fuse connection end 700 and the control connectionend 800 may be set to extend in a horizontal direction, and the fuseconnection end 700 and the control connection end 800 may be positionedon two opposite sides of the active region 200, respectively.

In this case, the fuse structure may also be provided with a sourceconnection end 910 connected to the source region 500 and a drainconnection end 920 connected to the drain region 600. Horizontalextension directions of the fuse connection end 700, the controlconnection end 800, the source connection end 910 and the drainconnection end 920 may be perpendicular to each other.

Referring to FIG. 3 and FIG. 4, when the extension direction of theactive region 200 is parallel to the surface of the substrate 100, andthe active region 200 is spaced apart from the substrate 100, the fuseconnection end 700 and the control connection end 800 may be set toextend along a direction on a horizontal plane perpendicular to theextension direction of the active region 200. In some embodiments, thefuse connection end 700 and the control connection end 800 may also beset to extend upward in a vertical direction (not shown), and so on.

It is to be understood here that while the fuse connection end 700 isconnected to the fuse gate layer 320, the fuse connection end 700 isinsulated and isolated from the control connection end 800. In someembodiments, an isolation layer 1000 may be provided between the fuseconnection end 700 and the control connection end 800 (referring to FIG.2 or FIG. 4). In this case, a thickness of the isolation layer 1000 maybe set to be greater than a preset thickness. That is, the isolationlayer 1000 is set to have a sufficiently large thickness, to prevent theadverse impact on the second gate dielectric layer 410 when the firstgate dielectric layer 310 is broken down. The preset thickness may beset according to actual situation.

In one embodiment, referring to FIG. 5, there is provided a method formanufacturing a fuse structure, including:

Step S100: providing a substrate 100;

Step S200: forming an active region 200 on the substrate 100;

Step S300: forming a fuse gate structure 300 on a circumferential outersurface of the active region 200, wherein the fuse gate structure 300 iselectrically connected to a first power source; and

Step S400: forming a control gate structure 400 on a circumferentialouter surface of the fuse gate structure 300, wherein the control gatestructure 400 is electrically connected to a second power source.

A voltage of the first power source is greater than that of the secondpower source.

In some embodiments, in an application process of the fuse structureformed by means of the method of this embodiment, reading differentlogic states “0” and “1” of the fuse structure may be implemented bycontrolling ON and OFF of the first power source.

In addition, a reasonable second power source may be set, such that whenvarious logic states of the fuse structure are read to turn on thesecond power source, a conductive channel is formed in the active region200, and then the logic states “0” and “1” are read based on differentsource-drain currents.

It is worth noting that in the present disclosure, the fuse gatestructure 300 being electrically connected to the first power sourcemeans that the fuse gate structure 300 has the function of electricallyconnecting the first power source. However, in practical applications,it is needed to determine whether to obtain electrical signal connectionaccording to requirements. In some embodiments, a first switch may beprovided between the fuse gate structure 300 and the first power source.

Similarly, the control gate structure 400 being electrically connectedto the second power source means that the control gate structure 400 hasthe function of electrically connecting the second power source.However, in practical applications, it is needed to determine whether toobtain electrical signal connection according to requirements. In someembodiments, a second switch may be provided between the control gatestructure 400 and the second power source.

In this embodiment, the fuse gate structure 300 surrounds thecircumferential outer surface of the active region 200, and the controlgate structure 400 surrounds the circumferential outer surface of thefuse gate structure 300, such that the conductive channel may be formedin the circumferential outer surface of the active region 200, and thusarea can be effectively saved. Meanwhile, the control gate structure 400and the fuse gate structure 300 are stacked and arranged around, therebybeing combined into a single gate structure, so this embodiment cangreatly save area and greatly improve integration of a fuse circuit.

In one embodiment, the extension direction of the active region 200 isperpendicular to the surface of the substrate 100, and the active region200 is connected to the substrate 100.

In this case, in some embodiments, before Step S200, the method mayinclude: forming a source region 500 (or a drain region 600) in thesubstrate 100 by means of ion implantation or the like. Next, the activeregion 200 is formed on the source region 500 (or the drain region 600)in Step S200. After Step S200, the drain region 600 (or the sourceregion 500) may be formed on a top of the active region 200.

In one embodiment, the extension direction of the active region 200 isparallel to the surface of the substrate 100, and the active region 200is spaced apart from the substrate 100.

In this case, in some embodiments, after Step S200, epitaxial growth maybe performed on two sides of the active region 200 to form the sourceregion 500 and the drain region 600.

In one embodiment, Step S300 includes:

Step S310: forming a first gate dielectric layer 310 on thecircumferential outer surface of the active region 200; and

Step S320: forming a fuse gate layer 320 on a circumferential outersurface of the first gate dielectric layer 310, wherein the fuse gatelayer 320 and the first gate dielectric layer 310 constitute the fusegate structure 300.

In this case, Step S400 includes:

Step S410: forming a second gate dielectric layer 410 on acircumferential outer surface of the fuse gate layer 320; and

Step S420: forming a control gate layer 420 on a circumferential outersurface of the second gate dielectric layer 410, wherein the controlgate layer 420 and the second gate dielectric layer 410 constitute thecontrol gate structure 400.

In one embodiment, the thickness of the first gate dielectric layer 310is smaller than that of the second gate dielectric layer 410.

In one embodiment, after Step S420, the method also includes:

Step S500: forming a fuse connection end 700 connected to the fuse gatelayer 320, wherein the fuse connection end 700 is configured toelectrically connect the first power source; and

Step S600: forming a control connection end 800 connected to the controlgate layer 420, wherein the control connection end 800 is configured toelectrically connect the second power source.

The fuse connection end 700 and the control connection end 800 arerespectively positioned on two opposite sides of the active region 200.

In one embodiment, an extension direction of the fuse connection end 700and an extension direction of the control connection end 800 areperpendicular to the extension direction of the active region 200.

Reference may be made to the limitations on the fuse structure forlimitations and technical effects of the method for manufacturing a fusestructure, and thus their detailed descriptions are omitted here.

It is to be understood that although the various steps in the flowchartof FIG. 5 are displayed in sequence as indicated by the arrows, thesesteps are not necessarily performed in sequence in the order indicatedby the arrows. It should be understood that unless expressly statedherein, the execution of these steps is not strictly limited insequence, and these steps may be performed in other orders. Moreover, atleast a part of the steps in FIG. 5 may include a plurality of steps ora plurality of stages, which are not necessarily performed at the samemoment, but may be executed at different moments, and the order ofexecution of these steps or stages is not necessarily performedsequentially, but may be performed alternately or alternately with atleast a part of the steps or stages of other steps or other steps.

Technical features of the above embodiments may be arbitrarily combined.For simplicity, all possible combinations of the technical features inthe above embodiments are not described. However, as long as thecombination of these technical features is not contradictory, it shallbe deemed to be within the scope recorded in this specification.

The above embodiments merely express a plurality of implementations ofthe present disclosure, and descriptions thereof are relatively concreteand detailed. However, these embodiments are not thus construed aslimiting the patent scope of the present disclosure. It is to be pointedout that for persons of ordinary skill in the art, some modificationsand improvements may be made under the premise of not departing from aconception of the present disclosure, which shall be regarded as fallingwithin the scope of protection of the present disclosure. Thus, thescope of protection of the present disclosure shall be subject to theappended claims.

What is claimed is:
 1. A fuse structure, comprising: a substrate; anactive region positioned above the substrate; a fuse gate structuresurrounding a circumferential outer surface of the active region andelectrically connected to a first power source; and a control gatestructure surrounding a circumferential outer surface of the fuse gatestructure and electrically connected to a second power source; wherein,a voltage of the first power source is greater than that of the secondpower source.
 2. The fuse structure according to claim 1, wherein anextension direction of the active region is perpendicular to a surfaceof the substrate, and the active region being connected to thesubstrate.
 3. The fuse structure according to claim 1, wherein anextension direction of the active region is parallel to a surface of thesubstrate, and the active region being spaced apart from the substrate.4. The fuse structure according to claim 1, wherein the fuse gatestructure comprises a first gate dielectric layer and a fuse gate layer,the first gate dielectric layer surrounding the circumferential outersurface of the active region, the fuse gate layer surrounding acircumferential outer surface of the first gate dielectric layer andbeing electrically connected to the first power source; and the controlgate structure comprises a second gate dielectric layer and a controlgate layer, the second gate dielectric layer surrounding acircumferential outer surface of the fuse gate layer, the fuse gatelayer surrounding a circumferential outer surface of the second gatedielectric layer and being electrically connected to the second powersource.
 5. The fuse structure according to claim 4, wherein a thicknessof the first gate dielectric layer is smaller than that of the secondgate dielectric layer.
 6. The fuse structure according to claim 4,wherein the fuse structure further comprises a fuse connection end and acontrol connection end, the fuse connection end being connected to thefuse gate layer and being configured to electrically connect the firstpower source, the control connection end being connected to the controlgate layer and being configured to electrically connect the second powersource; and the fuse connection end and the control connection end arerespectively positioned on two opposite sides of the active region. 7.The fuse structure according to claim 6, wherein an extension directionof the fuse connection end and an extension direction of the controlconnection end are perpendicular to the extension direction of theactive region.
 8. The fuse structure according to claim 1 furthercomprising a source region and a drain region, wherein in the extensiondirection of the active region, the source region and the drain regionsare respectively connected to two sides of the active region.
 9. Amethod for manufacturing a fuse structure, comprising: providing asubstrate; forming an active region above the substrate; forming a fusegate structure on a circumferential outer surface of the active region,the fuse gate structure being electrically connected to a first powersource; and forming a control gate structure on a circumferential outersurface of the fuse gate structure, the control gate structure beingelectrically connected to a second power source; wherein, a voltage ofthe first power source is greater than that of the second power source.10. The method for manufacturing a fuse structure according to claim 9,wherein an extension direction of the active region is perpendicular toa surface of the substrate, the active region being connected to thesubstrate.
 11. The method for manufacturing a fuse structure accordingto claim 9, wherein an extension direction of the active region isparallel to a surface of the substrate, the active region being spacedapart from the substrate.
 12. The method for manufacturing a fusestructure according to claim 9, wherein the forming a fuse gatestructure on a circumferential outer surface of the active regioncomprises: forming a first gate dielectric layer on the circumferentialouter surface of the active region; forming a fuse gate layer on acircumferential outer surface of the first gate dielectric layer, thefuse gate layer and the first gate dielectric layer constituting thefuse gate structure; and the forming a control gate structure on acircumferential outer surface of the fuse gate structure comprises:forming a second gate dielectric layer on a circumferential outersurface of the fuse gate layer; and forming a control gate layer on acircumferential outer surface of the second gate dielectric layer, thecontrol gate layer and the second gate dielectric layer constituting thecontrol gate structure.
 13. The method for manufacturing a fusestructure according to claim 12, wherein a thickness of the first gatedielectric layer is smaller than that of the second gate dielectriclayer.
 14. The method for manufacturing a fuse structure according toclaim 12, wherein after forming a control gate layer on acircumferential outer surface of the second gate dielectric layer, themethod further comprises: forming a fuse connection end connected to thefuse gate layer, the fuse connection end being configured toelectrically connect the first power source; and forming a controlconnection end connected to the control gate layer, the controlconnection end being configured to electrically connect the second powersource; wherein the fuse connection end and the control connection endare respectively positioned on two opposite sides of the active region.15. The method for manufacturing a fuse structure according to claim 14,wherein an extension direction of the fuse connection end and anextension direction of the control connection end are perpendicular tothe extension direction of the active region.
 16. The method formanufacturing a fuse structure according to claim 9, wherein beforeforming the active region above the substrate, the method furthercomprises: forming a source region in the substrate by means of ionimplantation; the forming the active region above the substratecomprises: forming the active region on the source region.
 17. Themethod for manufacturing a fuse structure according to claim 16, whereinafter forming the active region above the substrate, the method furthercomprises: forming a drain region on a top of the active region.
 18. Themethod for manufacturing a fuse structure according to claim 9, whereinbefore forming the active region above the substrate, the method furthercomprises: forming a drain region in the substrate by means of ionimplantation; and the forming the active region above the substratecomprises: forming the active region on the drain region.
 19. The methodfor manufacturing a fuse structure according to claim 18, wherein afterforming the active region above the substrate, the method furthercomprises: forming a source region on a top of the active region. 20.The method for manufacturing a fuse structure according to claim 17,after forming the active region above the substrate, the method furthercomprises: performing epitaxial growth on two sides of the active regionto form the source region and the drain region.